1. Field of the Invention
The present invention relates to a method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor. In particular, the present invention relates to a method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor which can be used without limitation in thickness of a thin silicon/silicon germanium film used as a base film to self-align a base and a collector and is also not affected by the size and density of its pattern.
2. Description of the Prior Art
Recently, an attempt to improve performance of a heterojunction bipolar transistor has been actively made by giving a least process change in the silicon manufacture process now being used widely, instead of making the device and the circuit itself using a compound semiconductor. A typical one of them is a silicon/silicon germanium heterojunction bipolar transistor.
In FIG. 1, there is shown a cross sectional view of SSSB (Super Self-aligned Selectively grown Base) transistor fabricated by using silicon/silicon germanium as a base film, disclosed, in 1990, in IEDM by NEC. In order to make the silicon/silicon germanium heterojunction bipolar transistor having the above-mentioned structure, a N.sup.+ buried layer 2 is formed on a P.sup.- silicon substrate 1, and then a N.sup.- epitaxial layer 3 is formed on the N.sup.+ buried layer 2. Thereafter, after a device separation is performed, an oxide film 4, a P.sup.+ polysilicon silicon film 5 and an insulating film 6 are sequentially formed on the N.sup.- epitaxial layer 3. Then, the insulating film 6 and the P.sup.+ polysilicon silicon film 5 are sequentially etched by using emitter as a mask. Next, first side-wall insulating films 7 are formed through the insulating film deposition and etch-back method. The exposed portion of the oxide film 4 is wet-etched by using the insulating film 6 and the first side-wall insulating films 7 as an etching mask. At this time, the oxide film 4 is laterally etched by isotropic etch.
Thereafter, a silicon/silicon germanium film 8 is formed as a base film using the selective epitaxial growth method, second side-wall insulating films 9 are formed by the insulator deposition and etch-back method, and then a N.sup.+ polysilicon silicon film 10 is formed as an emitter electrode by means of the selective epitaxial growth method, thereby completing a SSSB transistor using the silicon/silicon germanium film 8 as a base film.
In FIG. 1, a reference numeral 8-1 indicates a base linker.
In case that the silicon/silicon germanium heterojunction bipolar transistor is manufactured by the above-mentioned method, assuming that the growth rate of the silicon/silicon germanium film 8 is the same in the N.sup.- epitaxial layer 3 and the P.sup.+ polysilicon silicon film 5 when the silicon/silicon germanium film 8 is formed as a base film by means of the selective epitaxial growth method, there occurs a problem that the thickness of the silicon/silicon germanium film 8 used as a base film must be more than one half of the oxide film 4 in thickness. In addition, since the base linker opening must be buried by means of the selective epitaxial growth method, there is a disadvantage that device performance uniformity is degraded within the wafer due to a loading phenomenon caused by the difference in the size and density of the pattern thereof.
FIG. 2 shows a structure of the heterojunction bipolar transistor disclosed in IDEM by Siemens AG 1995, in which it has the same problem as shown in FIG. 1 because the process of forming the silicon/silicon germanium film 16 is same with the process shown in FIG. 1. In addition, since the N.sup.+ epitaxial layer 11 is shaped like an island on a substrate and thus the step coverage becomes degraded in the subsequent process step 5, there occurs is a problem in forming multilevel interconnections thereon and also a limitation that the width W must be less than the width T in case that the oxide film 12 is etched along the side by means of selective wet etching, as shown in FIG. 2. Also, since the N.sup.- epitaxial layer 11 must be increased in thickness so as to make the collector-emitter breakdown voltage high, there is a disadvantage that the step coverage becomes further degraded, and the use of the device is thus limited to a low voltage device.
In FIG. 2, the reference numerals 13, 14, 15, 16-1, 17, and 18 indicate a P.sup.+ polycrystalline silicon, an oxide film, a first side wall insulating film, a base linker, a second side wall insulating film, and an N.sup.+ polycrystalline silicon, respectively.